The present invention relates to a designing analysis technique of an electric/electronic circuit (e.g., not only an electric circuit or a semiconductor integrated circuit but also an electronic circuit packaging the semiconductor integrated circuit) and, more particularly, to a static-dynamic timing analysis division sharing a static analysis and a dynamic analysis for a circuit to be subjected to the designing analysis (a circuit to be analyzed), a timing analysis method, and a storage medium stored with a program for causing a computer to execute the analysis method.
In the timing analysis of the electric/electronic circuit, a static timing analysis or both a dynamic timing analysis and a static timing analysis can be adopted in place of the dynamic timing analysis so as to improve the operating efficiency of the timing analysis.
The analysis flow adopting the aforementioned static timing analysis and dynamic timing analysis can be exemplified by a flow shown in FIG. 2. In FIG. 2: numeral 21 designates a circuit connection information to be analyzed; numeral 22 a timing designation and clock designation information of input/output signals; numeral 23 a conventional static timing analysis device; numeral 24 a signal information (pattern); numeral 25 a dynamic timing analysis device; and numeral 26 a circuit design phase. For the static timing analysis made in the static timing analysis device 23, basically, the signal information of the individual circuit elements by a simulation is not required, but the timing and clock designations 22 of the input/output signals are performed to find out the slowest path (or critical path) between latches, and a setup timing analysis is made on whether or not the signal transmission on that critical path is better in time than the clock cycle. In the static timing analysis, moreover, the fastest path is found out among the latches, and a hold timing analysis is made on whether or not next data are to be fetched at the timing of the same clock. In the dynamic timing analysis made in the dynamic timing analysis device 25, the signal information (or test pattern), as designated by 24, of the individual circuit elements by the simulation is required, and the circuit connection of the analyzed circuit is activated for the simulation by inputting the signal information to the input terminals of the circuit connection information, as designated by 21.
The timing analysis system for the electric/electronic circuit of the prior art is disclosed in Japanese Patent Laid-Open Nos. 198723/1998, 44590/1995 and 50499/1997, for example.
The technique, as disclosed in Japanese Patent Laid-Open No. 198723/1998, warrants the timing only by the static timing analysis for such one of the electric/electronic circuits as is provided in a mixed manner with a synchronous circuit synchronizing with a specific clock signal and an asynchronous circuit having no specific clock or failing to synchronize with the specific clock signal.
Japanese Patent Laid-Open No. 50449/1998 provides a technique for discriminating a synchronous circuit portion and an asynchronous circuit portion from a synchronous/asynchronous mixed circuit to make the static timing analysis for the discriminated synchronous circuit portion and the dynamic timing analysis for the discriminated asynchronous circuit portion.
In this technique of the publication, however, there is made neither a hazard (or spike noise) analysis for warranting the normal circuit operation at the synchronous circuit portion nor the application of the static timing analysis to the asynchronous circuit portion.
The circuit analysis system, as disclosed in Japanese Patent Laid-Open No. 44590/1995, decides whether or not a spike noise generating circuit is present in the circuit to be analyzed. However, the system is defective in that the analysis method is low in reliability.
In the timing analysis technique of the electric/electronic circuit, the static timing analysis of the prior art analyzes the timing of only a synchronous circuit of a designated clock. This makes it essential to designate the clocks individually. In the case of a hazard analysis for warranting the normal circuit operation at the synchronous circuit portion, moreover, the hazard analysis has to be made for the dynamic timing analysis by searching the portions individually. For the hazard analysis, it is insufficient to use the circuit analysis system, as disclosed in Japanese Patent Laid-Open No. 44590/1995.
Therefore, the timing analysis cannot be made unless it is possible to designate the clocks or to extract the circuit portion which may cause a hazard.
In this regard, we have clarified that when there is in an object circuit a clock generating circuit constructed of a circuit capable of being deemed as an arbitrary counter circuit, there arises a problem that it takes a long time to prepare the information for designating the clock and the instruction information for the setup analysis and hold analysis of the clock gate which has been frequently used in resent years for lowering the electric power. It has also been found that the analysis on whether or not the instruction information is correctly given for the aforementioned setup analysis and hold analysis cannot be made without analyzing the static timing analysis results to discriminate the pseudo errors manually thereby to take a number of steps for the analyses.
Moreover, the user has been required for inefficient works to select a circuit portion needing the hazard analysis of the synchronous circuit portion and to perform another operation for the circuit portion. It is less efficient to analyze the circuit portion requiring the hazard analysis manually. Even when the dynamic timing analysis method is used, there is required an inefficient work to teach the dynamic timing analysis device the circuit portion requiring the hazard analysis. It is thought that even the use of the circuit analysis system disclosed in Japanese Patent Laid-Open No. 44590/1995 is insufficient for pointing out the circuit portion requiring the hazard analysis.
An object of the invention is to provide a static-dynamic timing analysis method capable of making a highly reliable timing analysis efficiently and a storage medium stored with a program for causing a computer to execute the method.
Another object of the invention is to provide a static-dynamic timing analysis method capable of performing the extraction of the clock information of a synchronous/asynchronous mixed circuit efficiently and a storage medium stored with a program for causing a computer to execute the method.
Still another object of the invention is to provide a static-dynamic timing analysis method capable of performing the timing analysis considering the hazard occurrence probability in the synchronous/asynchronous mixed circuit efficiently and a storage medium stored with a program for causing a computer to execute the method.
A further object of the invention is to provide a static-dynamic timing analysis method capable of performing a highly reliable timing analysis considering the clock information and the hazard occurrence probability in the synchronous/asynchronous mixed circuit efficiently and a storage medium stored with a program for causing a computer to execute the method.